Answers for "full adder verilog test best"

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full adder verilog test best

module tb;
  reg a, b, cin;
  wire sum, cout;
  integer i;

  fa u0 ( .a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));

  initial begin
    a <= 0;
    b <= 0;

    $monitor("a=%0b b=%0b cin=%0b sum=%0b cout=%0b", a, b, cin, sum, cout);

    for (i = 0; i < 7; i = i + 1) begin
      {a, b, cin} = i;
      #10;
    end
  end
endmodule

Posted by: Guest on April-30-2021

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