switch case within process vhdl
p_CASE : process (r_VAL_1, r_VAL_2, r_VAL_3)
variable v_CONCATENATE : std_logic_vector(2 downto 0);
begin
v_CONCATENATE := r_VAL_1 & r_VAL_2 & r_VAL_3;
case v_CONCATENATE is
when "000" | "100" =>
r_RESULT <= 0;
when "001" =>
r_RESULT <= 1;
when "010" =>
r_RESULT <= 2;
when others =>
r_RESULT <= 9;
end case;
end process;case vhdl
case SEL is
when "01" => Z <= A;
when "10" => Z <= B;
when others => Z <= 'X';
end case;Copyright © 2021 Codeinu
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